What is Cadence Virtuoso?

Welcome back to the pip install series by the EA and HAM Club. This time we’re going to explore yet another useful software ‘Cadence Virtuoso’. We will understand its uses, installation and learn it using a simple example.

Cadence virtuoso is a very important EDA tool for electronics students learning about IC design/analysis and PCB design/analysis.

At undergraduate level, virtuoso is majorly used for custom design and analysis of circuits based on MOS technologies, especially in the CMOS VLSI course.

The Virtuoso System Design Platform allows IC designers to easily include system-level layout parasitics in the IC verification flow, enabling time saving by combining package/board layout connectivity data with the IC layout parasitic electrical model.

It enables engineers to design concurrently across chip, package, and board, saving time and minimizing errors. It is ideal for designs that integrate multiple heterogeneous ICs, including RF, analog, and digital devices.

Some key benefits of Cadence Virtuoso are:

1. Easy to use, easy to understand software with an interactive interface.
2. Supports circuit design by using symbols and structures in the workspace and also allows text based design.
3. Great platform for beginners in the core industry to start learning about design and synthesis.
4. Allows the user to analyze the designs on various parameters like power consumption, area usage and delay.

The process flow is as follows:

1. First we create a schematic view of the circuit by selecting circuit components present in the software. A text input can also be given in order to connect the components for forming a circuit. There are various libraries present in the software and one can choose from them according to the need of IC design. For example, we have a library which contains components of the 180 nm technology node, another with components of 90 nm technology node, and so on. Nowadays, we have much more updated libraries too.
2. Once the user is satisfied with the circuit design, he can move on to the simulation. This is the step where we use the tool to understand how this circuit will work in real life, if fabricated. The simulation gives us a lot of insights about our circuit and the way it works.
3. After the simulation is successfully completed, the user can analyse the reports that are generated in the software. One can know about the errors and possible warnings in the circuit, power consumption of the circuit, the time delay from input to output, etc.
4. At undergraduate level, designing custom MOS circuits and ICs is the major use of the software. But for post graduates and professionals, the software provides layout design features as well. There is the facility of ERC (Electronic Rule Check) and DRC (Design Rule Check) to make sure that the layout design is correct in all terms. LVS (Layout Versus Schematic) check is used to compare layout and schematic. All these functionalities are used in the industry.
5. After the user is satisfied with the layouts, we move on to post layout simulation. Netlists are generated and after a few more processes, the user can send the final design for fabrication. We can safely ignore those details at undergraduate level.

How to Download and Install the software?

Given is the google drive link to a Cadence Virtuoso IC Design 6.17 software installed on a Red Hat linux virtual machine.

Cadence IC Design Virtuoso 6.17

The original size of software is around 50GB (gigabytes) hence it has been compressed to 13 GB and split into 4 parts for ease of sharing.

For installation refer to the readme file given in the above drive link. It will also help you in setting up the software for first use.

Observing Input & Output characteristics of N-channel MOSFET using Cadence Virtuoso

We are starting off with a simple example to get familiar with this new tool. After following up with this tutorial one will be able to create a new library or a cell, add components, make appropriate connections and simulate a circuit with appropriate parameters to observe the outputs, both numerically and graphically. Let’s get started!

1)The software is running properly if you can see the window as given.

2)To create a new cell view : Click on File → New → Cellview

Select Library as gpdk180

Enter an appropriate name for cell (Example : nmos_char)

Click on OK

A new schematic editor window will appear.

3) To add a component:

Click on Create Instance button on the toolbar

Add instance window will appear

4) Click on Browse button

5) Select Library gpdk180, Cell as nmos, and double click on Symbol in View

6) When appropriate Library, Cell and View are selected click Hide on Add Instance Window

7) Place the component (nmos transistor instance) on the schematic sheet

8) Similarly place the following components from Add instance menu,

9) To connect wires Press w on keyboard (shortcut for wire) or select wire option from the toolbar

10) Make connections as given in the figure below

Important : Connect the body (bulk) of the transistor to ground.

11) To save the schematic, click on the Check and Save option in the top left corner of the window.

Now as the connections are done, we move onto simulations.

Transfer Characteristics:

1) Right Click on V0 instance, select Properties. Edit Object Properties window will appear. Set DC Voltage as 5 V.

Similarly set DC Voltage for V1 as x (variable voltage). Again Check and Save.

2) In the top left corner of window, go to Launch and Select ADE L

3) A new ADE L window will appear. Go to Variables, select Copy From CellView

It will copy the x variable of the V1 voltage source.

Set value of x as 0.

4) Then go to Analyses select Choose

5) Choose Analyses window will appear

Select Analysis as dc, select Save DC operating point, next select Design Variable checkbox, enter variable name as x, enter sweep range Start 0 and Stop 2.

Click on OK.

6) To plot output current as a function of V1 (Vgs) voltage, we need to select output. To do that, in ADE L window go to Outputs, then To be Plotted, then Select on design option.

7) Select the Drain node on the schematic as shown. The output node will be visible in the output section in the ADE L window.

8) Click on the Netlist and Run button.

9) Output will be observed as shown below.

From the output we can estimate the threshold voltage of nmos as somewhere around 0.4–0.5 V.

Output Characteristics:

To get the output characteristics, set the V1 (Vgs) voltage as variable (y) and make the V0 (Vds) as variable (x).

1.Similarly carry out the simulation in the ADE L window as we did for Transfer Characteristics. Variables → Copy From Cellview.

2. Set value of x as 100m and y as 700m.

3. Analyses → Choose → dc → Save DC Operating Point → Design Variable → Select Design Variable as x → Start 0 Stop 1 -> Select Sweep Type as Linear and Step Size as 0.01

4. Outputs → To be plotted → Select on Design → Click on Drain Node on Schematic

5. Till now we varied Vgs at a particular Vds. Now we also want to vary Vds to get output characteristics. For that we will run a parametric analysis.

6. In the ADE L window, go to Tools then Parametric Analysis.

7. Select variable as y, sweep it from 0.4V to 1V in auto step mode.

8. Click on Run Selected Sweeps Button

9. Output will be observed as shown

This Article is a part of the PIP INSTALL series by EA and HAM club at NIT, Warangal. If you are a software enthusiasts we have a good news for you, there are several more articles lined up to be posted. To stay updated, Subscribe to our Mailing letter and follow us on Linkedin, Instagram and Facebook