PIP Install — Vivado
This is the Fifth article after AutoCAD, of the series PIP INSTALL. If you want to know more about Vivado, checkout the additional resources we have included at the end of the article.
Introduction:
Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of hardware description language(HDL) designs. Vivado Design Suite provides a cohesive environment for design, verification, analysis and implementation of HDL Designs.
It supersedes Xilinx ISE with additional features for system on a chip development and high-level synthesis.Vivado represents a ground-up rewrite and re-thinking of the entire design flow (compared to ISE).Like the later versions of ISE, Vivado includes the in-built logic simulator.Vivado also introduces high-level synthesis, with a toolchain that converts C code into programmable logic.
Features of Vivado:
Vivado is an integrated design environment (IDE) with system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems.
Installation Guide:
Go to https://www.xilinx.com/support/download.html
Click on “Vivado Archive” in the left column.
Click on the “2019.1” version.
Scroll down to “Vivado Design Suite — HLx Editions — 2019.1 Full Product Installation”.
Click on the “ Vivado HLx 2019.1: WebPACK and Editions — Windows Self Extracting Web Installer”
You will be asked to either sign in or create an account.
Creating an account:
- Enter all the fields. Use college email for corporate email.
- Upon submission, you will receive an email with the access token.
- Enter the access token and create a password.
- You will be redirected to the sign in page. Sign in and continue.
You will land on the “Download Center — Name and Address Verification” page.
Fill in the required fields, and enter “NIT Warangal” for Company Name. Give college address details.
Click Download.
Run the Application.
Allow Access.
Continue with 2019.1 Version.
Click on Next. (You might have to resize the page to see the options at the bottom right.)
Enter User ID (email address you used for signing in) and password. Click Next.
Check all three “I Agree” boxes. Click Next.
Select “Vivado HL WebPack” and click Next.
Under Devices, uncheck “7 Series”, “UltraScale” and “UltraScale +”.
Click on the “+” next to “SoCs” and uncheck “Zynq UltraScale+ MPSoC”.
Click Next.
Click Next.
Click “Yes”. Click Next.
Click “Install”. It will start the installation process (~20 mins).
Click on “Install”.
Check the top box (allow private networks) and uncheck the bottom box (don’t allow public networks).
Installation done!
Tutorial: 4:1 Multiplexer
To get familiar with Vivado, we advise you to build this sample project. We have covered all the steps in detail.
Run the Vivado 2019.2 (by right click on your desktop shortcut) as administrator
In the Quick Start, Click on the Create project You will get the following window
Click on the Next Button
Enter your Project Name and click on the Next Button
Select RTL Project and click on the Next Button
Now Click on the + symbol and Create a file
Enter the name of the file and click on the ok button. After that you can see your file name in the list.Now click on the Next Button
We need not add any constraints so Click on the Next button.
Leave Everything to Default and Click on the Next button.
Finally Click on the Finish button. You have successfully created your first project.
Now you will be able to see the following window to define your module. Type Module name (mux_4to1) and the click on the ok button.Click on yes if window pops up
Double click on the mux_4to1(or any name you have given) in design sources and maximize the window opened on the right side.
Copy and paste the following code.
module mux_4to1(
input s0,
input s1,
input [3:0] I,
output out
);
assign out = s1?(s0?I[3]:I[2]):(s0?I[1]:I[0]);
endmodule
Click on the save button after pasting(*don’t forget*)
Now click on the Add Sources Button in left menu and click on add or create simulation sources and click on the Next button
Now Click on the + symbol and Create a file
Enter the name as mux_4to1_tb and click on the ok button.
Click the finish button
Type Module name (mux_4to1_tb) and the click on the ok button.Click on yes if window pops up
Click on the sources just right to the left menu to open up all the sources.Expand the simulation sources In it right click on mux_4to1_tb and click on set as top(this is to make mux_4to1_tb as top simulation source file)
Double click on mux_4to1_tb to open it.
Copy and paste the following code in mux_4to1_tb .
module mux_4to1_tb();
wire out;
reg s0,s1;
reg [3:0] I;
mux_4to1 u1 (s0,s1,I,out);
initial
begin
I=4'b1011;
s1=0;s0=0;
#10 s1=0;s0=1;
#10 s1=1;s0=0;
#10 s1=1;s0=1;
#10 I=4'b0001;
#10 s1=0;s0=0;
#10 s1=0;s0=1;
#10 s1=1;s0=0;
#10 s1=1;s0=1;
#10 $finish;
end
endmodule
Click on the save button
Now Click on Run Simulation Button in the left menu and run behavioral simulation
You can see the simulation result as the following image
Click on the Open Elaborated Design in left menu to see the schematics(click on ok if window pops up)
Some More Tutorials
XILINX Vivado tutorial | Create new project in Xilinx Vivado | Half adder design and simulation
References
https://en.wikipedia.org/wiki/Xilinx_Vivado
This Article is a part of the PIP INSTALL series by EA and HAM club at NIT, Warangal. If you are a software enthusiasts we have a good news for you, there are several more articles lined up to be posted. To stay updated, Subscribe to our Mailing letter and follow us on Linkedin, Instagram and Facebook
